1. Field of the Invention
This invention relates to a semiconductor memory device (EEPROM) having electrically rewritable and non-volatile semiconductor memory cells, specifically to a data write method thereof.
2. Description of Related Art
A NAND-type flash memory is known as one of EEPROMs (Electrically Erasable and programmable ROMs). A memory cell array of the NAND-type flash memory is formed of NAND cell units arranged therein. Each NAND cell unit has plural memory cells connected in series in such a manner that adjacent two memory cells share a source/drain layer.
Therefore, the NAND-type flash memory has features as follows: it is easy to increase the memory capacitance because the unit cell area of the memory cell array is smaller than that of a NOR-type EEPROM; and it is possible to perform substantially high-speed data read and write with such a scheme that data read and write is performed by a page.
To increase the data capacity of a NAND-type flash memory in comparison with currently used ones, it is used such a multi-value data storage scheme that one memory cell stores multi bits. For example, in a four-value data storage scheme, four-value data “xy” is used, which is defined by upper page data “x” and lower page data “y”.
Four-value data “xy” is, for example, as shown in FIG. 4, defined as that “11”, “10”, “00” and “01” are assigned in order of cell's threshold voltage. Data “11” is an erased state where the cell is set in a negative threshold voltage state. Data “10” may be written with selectively writing lower page data “y” (=“0”) into the erased state memory cells while data “00” and “01” may be written with selectively writing upper page data “x”(=“0”) into memory cells with data “10” and “11”, respectively (for example, refer to Unexamined Japanese Patent Application Publication No. 2001-93288).